---
title: 单板设计建议
description: "BMC模组板的SerDes参考时钟模块内部集成了耦合电容，因此单板PCB上可以不集成耦合电容，需要满足PCIe时钟典型应用电气特性的电气参数要求。"
url: https://www.hikunpeng.com/document/detail/zh/kunpengmodule/S920L08/bmchg/S920L08_BMC_41_0011.html
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indexId: 8b5f1b51f6680e343b30f3ae1794dfa4ca74b787fda3a11389a912871b572e6163
---
# 单板设计建议

BMC模组板的SerDes参考时钟模块内部集成了耦合电容，因此单板PCB上可以不集成耦合电容，需要满足PCIe时钟典型应用电气特性的电气参数要求。


**表1 PCIe时钟典型应用电气特性**

| 符号 | 参数 | 最小值 | 典型值 | 最大值 | 单位 | 说明 |
| --- | --- | --- | --- | --- | --- | --- |
| FREF | Reference clock frequency | \- | 100 | \- | MHz | \- |
| FREF\_OFFSET | Reference clock frequency offset | \-300 | \- | 300 | ppm | \- |
| RMSJREF\_CLK | Reference clock random jitter (RMS) | \- | \- | \- | ps | 参考PCIe协议 |
| DJREF\_CLK | Reference clock cycle to cycle jitter | \- | \- | \- | ps | 参考PCIe协议 |
| DCREF\_CLK | Duty cycle | 45 | 50 | 55 | % | \- |
| VCMREF\_CLK | Common mode input level | 0 | \- | vp | V | Differential inputs |
| VDREF\_CLK | Differential input swing | 0.3 | \- | \- | Vpp | Differential inputs |
| VOLREF\_CLK | Single\-ended input logic low | \-0.3 | \- | 0.3 | V | If single\-ended input is used |
| VOHREF\_CLK | Single\-ended input logic high | vp\-0.3 | \- | vp+0.3 | V | If single\-ended input is used |
| SWREF\_CLK | Input edge rate | 0.4 | \- | 4 | V/ns | \- |
| vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V | vp：PHY analog and digital supply, 0.9V |


还需满足以下要求：

- VDREF_CLK/4 + VCMREF_CLK <= vp
- VCMREF_CLK - VDREF_CLK/4 >= 0


图1 SerDes参考时钟单板集成耦合电容单板设计参考