Secure Memory Specifications

Figure 1 shows the memory channel usage of CPU 0. The TaiShan server has two CPUs, that is, socket 0 and socket 1. The previous figure presents the socket 0 information. Each CPU has two Totem dies, as shown in the red boxes.

Each die can have eight DIMMs in four channels. By default, intra-die memory interleaving is enabled and inter-die memory interleaving is disabled. If you need to enable inter-die memory interleaving, manually enable it in the BIOS. When inter-die interleaving is enabled, the two dies must have the same number of memory channels and the same memory size.

The current version has the following restrictions on secure memory:

1. The secure memory must be smaller than the total physical memory. Part of the secure memory must be reserved for the REE (for the BIOS and OS).
2. The secure memory must be smaller than the size of a memory space decoder (MSD) window.
3. If 3-way + 6-way memory interleaving is enabled, the BIOS applies for 3 secure memory segments with the same offset size. The secure memory size must be less than one-third of the MSD window.
4. Considering the impact of inter-socket interleaving on performance, the secure memory should be allocated from the memory space of a single CPU.

The MSD window varies according to the number of DIMMs. Table 1 describes the mapping if each single DIMM in a die is 32 GB.

When there is more than one MSD window, the system attempts to allocate secure memory from the smallest MSD window first. If the secure memory cannot be allocated from that window, the system tries the second smallest MSD window. Avoid 3-way + 6-way memory interleaving (which may cause memory waste). Configure 2, 4, or 8 DIMMs.