Redis jemalloc Memory Library Acceleration
Application scenario: RPUSH command in a Redis 2C2T container
Technical principle: With the Arm-based TBI feature enabled, the CPU ignores the most significant byte (bits[63:56]) of a 64-bit virtual address during address translation, and uses only the lower bits for addressing. This allows the upper eight bits of a pointer to be used by user software for storing additional information without affecting the actual memory access. This feature leverages the TBI mechanism to optimize jemalloc's size-class-index acquisition. Originally, jemalloc accessed the global rtree structure for this information, which is prone to cache misses and other issues. After the optimization, the size class index is encoded into the upper eight bits of the pointer, bypassing the access to the global rtree structure. This accelerates acquisition and boosts the overall memory allocation performance.
Performance metric: RPUSH throughput is improved by 5% in a 2C2T container Redis 7.0.15.
