IPI Latency Optimization for High-Specification VMs

In high-specification AArch64 KVM VMs, the delivery latency of inter-processor interrupts (IPIs) is significantly higher than in physical machines. This has become a key bottleneck affecting the multi-core communication performance of VMs. This issue stems from two primary factors: (1) the inefficiency of the software-generated interrupt (SGI) distribution path on the kernel side, and (2) VMs' lack of awareness of the actual host cache topology.

On the kernel side, when the guest OS sends an SGI to the target vCPU by writing the ICC_SGI1R_EL1 register, KVM needs to calculate the target Multiprocessor Affinity Register (MPIDR) based on the affinity information and then traverse all vCPUs for matching. The time complexity is O(n). IPI delivery latency per operation increases with the number of vCPUs. This feature pre-calculates a compressed mapping table from MPIDR values to vCPU indexes when a VM runs for the first time. In this way, the SGI distribution path traversal (time complexity: O(n)) is optimized to direct search (time complexity: O(1)), eliminating the performance bottleneck on the delivery path.

By default, a VM cannot obtain the actual cache topology information of the host machine. As a result, the guest OS kernel scheduler cannot correctly identify the core cluster level (CCL) scheduling domain and may schedule tasks that require frequent communication to vCPUs across CCLs, thus causing a large amount of cross-CCL IPI communication. This feature allows the actual cache topology of the host machine (including the level-specific cache capacity, sets, associativity, line size, and sharing level) configured at the QEMU/libvirt layer to be transparently transmitted to VMs. In this way, the guest OS kernel can establish an accurate CCL scheduling domain and preferentially schedule tasks to vCPUs at the same CCL, thus cutting the cross-CCL IPI communication traffic and further reducing the IPI latency.