EDA

Scenarios

Electronic design automation (EDA) refers to the use of computer-aided software to manage the entire process of integrated circuit (IC) development. This workflow spans from initial design (including schematic capture, layout implementation, and design rule checks) to functional and physical verification, and finally, manufacturing preparation.

IC design is highly complex and demands immense simulation and computing power. As advanced manufacturing nodes continue to evolve, design complexity grows exponentially, significantly increasing the need for high-performance computing. The tape-out stage is particularly critical. It involves processing and verifying massive amounts of physical data with highly compute-intensive workloads, posing a major challenge to EDA tool performance. At this stage, EDA tools must fully verify the chip layout to ensure it meets manufacturing design rules and yield requirements.

Currently, the global EDA market is dominated by three major players: Synopsys, Cadence, and Siemens EDA (formerly Mentor Graphics). These companies provide complete ASIC design toolchains and end-to-end solutions, covering everything from front-end design to back-end implementation and final sign-off.

In recent years, China's EDA industry has entered a period of accelerated growth. Local companies such as Empyrean Technology, Primarius Technologies, Cellix, and SMIT have achieved technical breakthroughs in several key areas. They are gaining influence in the Chinese market and are steadily building a self-reliant EDA ecosystem.

Challenges

• High computing intensity: In analog circuit simulation, solving the linear equation system Ax = b accounts for over 90% of the total runtime. The core computing kernel relies on LU decomposition of sparse matrices (using double-precision floating-point arithmetic). With an algorithmic complexity of N^3, it places extreme demands on computing resources.
• High memory access pressure: Sparse matrix structures lead to poor data locality and low data reuse, resulting in a low compute-to-memory ratio. Memory access patterns are primarily irregular, meaning system performance is severely limited by memory bandwidth.
• Difficult parallel acceleration: There are significant strong scaling bottlenecks, and parallelization becomes increasingly difficult as circuit scale grows. Specifically, coupled matrices contain serial critical paths that cannot be parallelized, creating a performance ceiling. Furthermore, the overhead of switching between serial and parallel segments is typically around 1 millisecond. This requires global synchronization for every fine-grained iteration, which severely restricts parallel acceleration efficiency.