Hydra Architecture Model

The Hydra model defines the data processing flow (package) of the hardware. This processing flow comprises a set of hardware-supported packet control stages (parsers & pipes). For details about the relationship between the stages, see Figure 1.

Figure 1 Packet control stages in the processing flow

package TX_OVS<IH>(
    Parser<IH> parse,
    Pipe<IH> mainPipe,
    Pipe<IH> postPipe);
package RX_OVS<IH>(
    Parser<IH> parse,
    Pipe<IH> mainPipe,
    Pipe<IH> postPipe);
package Switch<TH, RH>(TX_OVS<TH> tx, RX_OVS<RH> rx);

Each package contains one parser and two controls.

• The parser processes input data packets and converts the raw bitstream into structured protocol headers based on user-defined parsing rules, facilitating subsequent table lookup and action execution.

  parser Parser<H>(packet_in buffer, out H parsed_hdr); 

• Controls are core components used to define data packet processing logic. They operate on the headers extracted by the parser, executing corresponding actions based on table lookup results to implement functions such as packet forwarding, modification, or dropping.

  control Pipe<H>(in H hdr);

The pre-control (mainPipe) and post-control (postPipe) can define different tables and actions. The pre-control defines pre-auxiliary tables and main tables, and the post-control can define only post-auxiliary tables. For details, see Controls.

• Example 1: If you need to process packets in the receive (RX) direction only, instantiate the RX_OVS package.
  RXParser(), RXMainPipe(), and RXPostPipe() are the implementations of the parser, pre-control, and post-control.

  RX_OVS(
      RXParser(),
      RXMainPipe(),
      RXPostPipe()
  ) main;

• Example 2: If both the transmit (TX) and RX processes need to be included, instantiate the Switch package.

  Switch(
      TX_OVS(TXParser(),TXMainPipe(),TXPostPipe()),
      RX_OVS(RXParser(),RXMainPipe(),RXPostPipe())
  ) main;

• RX direction: Packets from the network.
• TX direction: Packets from the host.