Logical Architecture

This section introduces the logical architecture and acceleration principles of the KAE.

Figure 1 shows the logical architecture of the KAE.

Figure 1 Logical architecture

Table 1 describes the functions of each subsystem. The chip accelerator subsystem, BIOS subsystem, and BMC subsystem are equipped with the server hardware based on the Kunpeng 920 processor.

**Table 1** Subsystem functions
Subsystem	Function Description
Application systems	A user-plane system invokes the application library subsystem or driver subsystem to accelerate big data and web applications.
Application library subsystem	The application library subsystem includes the OpenSSL accelerator engine, zstd replacement library, LZ4 replacement library, and zlib replacement library, and provides standard interfaces to the upper layer.
Accelerator driver subsystem	This is the core part of the system and provides a unified driver interface for each accelerator module to the upper layer.
Chip accelerator subsystem	This subsystem is integrated on Kunpeng 920 series processors as an accelerator. It provides register interfaces for the upper layer. It is not open to users.
BIOS subsystem	The BIOS software system on a board determines the modules to be initialized based on the license and reports Advanced Configuration and Power Interface (ACPI) tables of the accelerator to the kernel for the accelerator driver subsystem to process.
BMC subsystem	This is a BMC software system, which manages accelerator licenses for servers.