Large System Extensions Compilation Instructions

In the case of multiple cores and severe atomic lock contention, add the Large System Extensions (LSE) options to the GCC compiler options to ease lock contention.

Load-link/Store-conditional (LL/SC) atomic instructions load shared variables to the L1 cache where the current core is located and modify them. The performance is good when there is little lock contention. In an intense lock contention scenario, the performance deteriorates severely. The Armv8.1 specification introduces a new atomic operation instruction extension LSE, which puts computation operations into the L3 cache to increase the scope of data sharing, reduce cache consistency time consumption, and improve lock performance when lock contention is intense.

LL/SC instructions (ldaxr and stlxr):

LSE instruction (ldaddal):

In the MySQL source package, the -march=armv8-a+lse compiler option can be added to the CMakeLists.txt file to use the atomic instruction extension LSE for performance optimization.