Cache Line Alignment Optimization

In multi-concurrency programming, the critical area variable features high write frequency. For example, the lockword in a lock changes the status continuously due to lock-up and lock release operations. Each change causes the CACHE_LINE in other cores to become invalid. To avoid interference between such data structure and other variables, the cache line is aligned in the application so that the variable exclusively occupies a cache line.

**Table 1** Sizes of cache lines at different levels on different platforms
Cacheline/Byte	x86	Kunpeng 920
L1	64	64
L2	64	64
L3	64	128

MySQL has made a number of 64-byte-aligned cache lines on the x86 platform. The L3 cache line of Huawei Kunpeng 920 processor is 128-byte. Therefore, the alignment in the MySQL source code needs to be changed to 128-byte. The modified alignment data structure is as follows:

brt_search_latches btr_search_sys

ReadView::m_view_list

trx_sys_t::rw_trx_list

trx_sys_t::mysql_trx_list

trx_sys_t::rsegs

srv_conc_t::n_active

lock_sys_t::mutex

lock_sys_t::wait_mutex

The 64-byte-aligned data structure in MySQL is changed to 128-byte-aligned data structure.

After the change, the TPM percentage increases to 3% to 4%.

Parent topic: MySQL