Architecture Difference
Pay attention to the difference of memory ordering models between different architectures.
Table 1 lists the memory ordering differences between x86 and Arm.
Out-of-Order Execution |
x86 |
Arm |
|---|---|---|
Read-read |
Not allowed |
Allowed |
Read-write |
Not allowed |
Allowed |
Write-read |
Allowed |
Allowed |
Write-write |
Not allowed |
Allowed |
Atomic operation-read and write |
Not allowed |
Allowed |
The out-of-order execution in Table 1 refers to a single memory access behavior in most cases.
Batch memory access behaviors, such as string processing instructions and non-volatile memory programming instructions in x86, are not within the scope of this document.
The following briefly describes the out-of-order execution behavior listed in Table 1.
Use the write-read out-of-order execution as an example. To access two global variables continuously, the operation sequence is to write a value to the global variable and then read the value of the other global variable as follows:
CPU 0 |
CPU 1 |
|---|---|
x = 1 r1 = y |
y = 1 r2 = x |
Initial value: x = 0 and y = 0 |
|
As shown in Table 1, write-read out-of-order execution exists in both the x86 and Arm architectures. Therefore, the actual execution sequence may be as follows:
CPU 0 |
CPU 1 |
|---|---|
r1 = y x = 1 |
r2 = x y = 1; |
Initial value: x = 0 and y = 0 |
|
Therefore, the final execution result may be r1 = 0 and r2 = 0.
Generally, the memory access sequence in the x86 architecture is much stricter than that in the Arm architecture. In most cases, the memory access sequence is fixed. If a multi-threaded program is ported to the Arm architecture without modification, function problems may occur.