Adjusting the Memory Page Size

Principle

The translation lookaside buffer (TLB) is the high-speed cache in the CPU for the page table that stores the mapping between the page addresses of the virtual addresses and the page addresses of the physical addresses. A higher TLB hit ratio indicates better page table query performance.

A TLB row is a page mapping relationship, that is, a page size of memory is managed.

Memory size managed by the TLB = Number of TLB lines x Memory page size.

The number of TLB lines of a CPU is fixed. Therefore, the larger the memory page is, the larger the managed memory is, and the higher the TLB hit rate in the same service scenario is.

On the Armv8 platform, the page size is usually set to 64 KB to improve the TLB hit ratio.

Procedure

1. Run the following command to check the memory page size. The default unit is B.

   getconf -a | grep PAGESIZE

   The following is an example of the output result.

   PAGESIZE       65536

Procedure

Before and after the modification, run the following command to check the TLB hit ratio ($PID indicates the process ID):

perf stat -p $PID -d -d -d

The command output contains the following information, in which 1.21% and 0.59% indicate the data miss ratio and instruction miss ratio respectively.

1,090,788,717      dTLB-loads                #  520.592 M/sec
13,213,603      dTLB-load-misses          #    1.21% of all dTLB cache hits
669,485,765      iTLB-loads                #  319.520 M/sec
3,979,246      iTLB-load-misses          #    0.59% of all iTLB cache hits

If the value of PAGESIZE is not 64 KB, modify the Linux kernel compilation options and recompile the kernel.

1. Run the following command to perform recompilation.

   make menuconfig

2. Set the value of PAGESIZE to 64 KB.

   Kernel Features-->Page size(64KB)

3. Compile and Install the Kernel