CPU Memory Fences

The x86-64 architecture provides three memory fences: (1) sfence; (2) lfence; (3) mfence.

sfence: ensures the in-order execution of write operations issued before and after the sfence instruction. Note that the write fence generally needs to be used in pairs with the read fence or data dependency fence.

lfence: ensures the in-order execution of read operations issued before and after the lfence instruction. Note that the read fence generally needs to be used in pairs with the write fence.

mfence: ensures the in-order execution of write and read operations issued before and after the mfence instruction.

• Code on x86:

  __asm__ __volatile__("sfence" : : : "memory"); 
  __asm__ __volatile__("lfence" : : : "memory"); 
  __asm__ __volatile__("mfence" : : : "memory");

• Alternative for Kunpeng processors:

  __asm__ __volatile__("dmb ishst" : : : "memory"); 
  __asm__ __volatile__("dmb ishld" : : : "memory"); 
  __asm__ __volatile__("dmb ish" : : : "memory");