Pipeline Orchestration Acceleration Instances
The following uses several examples to describe pipeline orchestration.
Eliminating Data Dependency
ADD x1, x2, x3 SUB x4, x1, x5
In the preceding code, the calculation of the SUB instruction depends on the result of the x1 register in the ADD instruction. Therefore, insert an empty instruction before the SUB instruction to wait for the SUB instruction to write the calculation result to the register file. After -mtune=tsv110 is added, the compiler adds two irrelevant instructions to eliminate data risks:
ADD x1, x2, x3 Instruction 1 Instruction 2 SUB x4, x1, x5
Eliminating Structure Dependency
ADD x1, x2, x3 SUB x4, x5, x6 LDR x6, [ x7, #12 ] SDR x6, [ x7, #12 ]
In the preceding code, the ADD and SUB instructions need to use ALU resources at the same time, and the LDR and STR instructions need to use MEM resources at the same time. Structure risks occur when the hardware cannot support the execution of multiple instructions at the same time. After -mtune=tsv110 is added, the compiler adds two irrelevant instructions to eliminate structure dependency.
ADD x1, x2, x3 Instruction 1 SUB x4, x5, x6 Instruction 2 LDR x6, [ x7, #12 ] Instruction 3 SDR x6, [ x7, #12 ]