Porting CPU Memory Barrier Instructions

In the x86-64 architecture, memory barrier instructions are classified into three types: sfence, lfence, and mfence.

• Write (store/release) instructions before and after the sfence instruction are executed in the instruction sequence before and after the sfence instruction. In terms of hardware, subsequent operations are performed only when all data in the store buffer is cleared.
• Read (load/acquire) instructions before and after the lfence instruction are executed in the instruction sequence before and after the lfence instruction.
• The write (store/release) instructions before the mfence instruction are executed before the write (store/release) instructions after the mfence instruction (instruction sequence, Program Order). This ensures data read and write in the instruction sequence.

__asm__ __volatile__("sfence" : : : "memory"); 
__asm__ __volatile__("lfence" : : : "memory"); 
__asm__ __volatile__("mfence" : : : "memory");

Replace the code as follows on the Kunpeng platform:

__asm__ __volatile__("dmb ishst" : : : "memory"); 
__asm__ __volatile__("dmb ishld" : : : "memory"); 
__asm__ __volatile__("dmb ish" : : : "memory");